Digital electronic devices typically include volatile and/or non-volatile electronic memory for program and data storage. There is a wide variety of electronic memory including Random Access Memory (RAM), Read-Only Memory (ROM), and/or Flash memory. Competition in the market for digital electronic devices demands ever increasing speed and decreasing power consumption. Read and write times in electronic memory are important performance parameters having a significant impact on electronic device speeds.
There are many sources of operational delay in NAND memory devices such as wait times between operations. For example, NAND memory device operations involve frequent ramping up and/or ramping down of internal nodes such as wordlines and bitlines. Voltage regulators pull up and/or down such internal nodes. Conventionally, an on-chip controller needs to wait until the ramping is complete for one event before beginning the next event. Further, capacitive loadings of such internal nodes depend on device operation modes. Ramping delays also depend on process variations, supply voltages and temperature conditions. Moreover, 3D (three dimensional) NAND memory devices have even larger capacitive loadings on wordlines and other internal nodes. On-chip charge pumps take time to increase tower voltages to the required higher voltages. To perform operations, internal nodes need significant time to reach “flat-top” voltage, and the amount of time needed can vary significantly for different operation modes and operating conditions. Controllers traditionally manage wait times with trimmable delays. Conventionally, delay trims settings are computed based on testing simulation and device characterization results, and account for worst case conditions. Thus, under nominal or fast conditions, even when internal voltage ramping is completed a controller will wait for the delay determined by trim settings based on a worst case condition. Thus, trimmable delay settings can negatively impact performance times under nominal or better than worst case conditions by increasing average NAND tR (read time) and tProg (write time) parameters.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.